Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
In multi-core microprocessor systems, each silicon die processor may contain multiple processing elements (“cores”). These cores may have the ability to parallel process vast amounts of data, using algorithms that may be diversified per core. Some algorithms require that threads of execution (“threads”) execute in parallel on multiple cores in a cooperative manner. In these situations, sharing of data may be essential.
One way to support sharing of data between threads executing on multi-core microprocessors is to supply each core with a respective cache coherent memory mechanism, which may include a cache and a cache controller. Generally, these mechanisms work in hardware to maintain the status of main memory that may be present in one or more of the core's caches.
Two classes of schemes may be utilized to maintain cache coherence, namely bus snoop schemes and coherence directory schemes. In bus snooping cache coherence schemes, the cache controller in each core of the processor monitors an interconnect, couples the processor to a memory to detect writes to and reads from the memory, and then updates the corresponding cache lines accordingly. The bus snooping scheme operates under the assumption that the interconnect is globally-observable by all of the cache controllers. The present disclosure appreciates that such interconnects do not scale well, and may not support multi-core microprocessors with a large number of cores per die, such as in excess of 16 cores per die.
The second cache coherence scheme employs a coherence directory scheme that is maintained either in main memory or in a combination of main memory and the individual caches. Entries (“descriptors”) in this coherence directory store the status of respective sets of memory locations, such as cache-line-sized rows of main memory. The status information stored in the descriptors may include, for example, whether a particular cache-line-sized row of main memory is cached in a particular set of caches.